In modern integrated circuits, such as circuits for mixed-mode and radio frequency applications, a pair of capacitors with a specific capacitance ratio (often referred to as 1:N capacitors, wherein N is an integer greater than zero) is often needed. The ratio of capacitances typically needs to have high accuracy for the integrated circuit to work accurately. For example, in analog/digital (A/D) converters, the accuracy of the capacitor pair determines the accuracy of the resulting digital signals, and thus a very high accuracy of capacitance ratio is required.
FIG. 1 illustrates a conventional circuit for providing 1:N capacitor pairs. The circuit includes an array of unit capacitors designed to have identical capacitances. An X-decoder and a Y-decoder are connected to the capacitor array and are used to select a number of unit capacitors from the capacitor array. By parallel connecting the selected unit capacitors, capacitors with greater capacitances can be formed. The exemplary array illustrated in FIG. 1 has nine unit capacitors, and thus can be used to achieve any ratio between 1:1 and 1:9, wherein the number 1 represents one unit capacitor, and the number 9 represents a capacitor formed by parallel connecting all nine unit capacitors.
The circuit illustrated in FIG. 1 has the advantageous feature of being able to dynamically provide a capacitor pair. However, some drawbacks limit its usage. For example, the formation of the capacitor array is process sensitive. Although all the unit capacitors are designed to be identical, some of the unit capacitors may be physically close to a pattern-sparse region, and some other unit capacitors may be physically close to a pattern-dense region. As a result, the capacitances of the unit capacitors have variations, which affect the accuracy of the capacitor pairs. Typically, capacitor arrays with greater numbers of unit capacitors have greater capacitance variations.
An additional drawback is that the X-decoder and Y-decoder consume chip area. Particularly, for 1:N capacitors wherein N is small, the chip area penalty is significant compared to the relatively small area occupied by the unit capacitors. Accordingly, capacitor pairs with improved accuracy and less chip area penalty are required.